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hmmmm_avr_generic/manifest_src/instructions.json

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[
{
"mnemonic": "ADC",
"description": "Adds two registers and the contents of the C flag and places the result in the destination register Rd. Rd ← Rd + Rr + C\nPC ← PC + 1",
"opcode": {
"base": "0001110000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rd + Rr + C",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a carry from bit 3; cleared otherwise.",
"op": "Rd3 & Rr3 | Rr3 & ((~R3)&1) | ((~R3)&1) & Rd3"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & Rr7 & ((~R7)&1) | ((~Rd7)&1) & ((~Rr7)&1) & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if there was a carry from the MSB of the result; cleared otherwise.",
"op": "Rd7 & Rr7 | Rr7 & ((~R7)&1) | ((~R7)&1) & Rd7"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "ADD",
"description": "Adds two registers without the C flag and places the result in the destination register Rd. (i) Rd ← Rd + Rr\nPC ← PC + 1",
"opcode": {
"base": "0000110000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" (i) Rd ← Rd + Rr",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a carry from bit 3; cleared otherwise.",
"op": "Rd3 & Rr3 | Rr3 & ((~R3)&1) | ((~R3)&1) & Rd3"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & Rr7 & ((~R7)&1) | ((~Rd7)&1) & ((~Rr7)&1) & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if there was a carry from the MSB of the result; cleared otherwise.",
"op": "Rd7 & Rr7 | Rr7 & ((~R7)&1) | ((~R7)&1) & Rd7"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "ADIW",
"description": "Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates\non the upper four register pairs and is well suited for operations on the Pointer Registers.\nThis instruction is not available on all devices. Refer to Appendix A. R[d+1]:Rd ← R[d+1]:Rd + K\nPC ← PC + 1",
"opcode": {
"base": "1001011000000000",
"mask": "1111111100000000"
},
"args": [
{
"name": "d",
"mask": "0000000000110000",
"limits": "d ∈ {24,26,28,30}"
},
{
"name": "K",
"mask": "0000000011001111",
"limits": " 0 ≤ K ≤ 63"
}
],
"ops": [
" R[d+1]:Rd ← R[d+1]:Rd + K",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "((~Rdh7)&1) & R15"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R15"
},
{
"flag": "Z",
"description": "Set if the result is 0x0000; cleared otherwise.",
"op": "((~R15)&1) & ((~R14)&1) & ((~R13)&1) & ((~R12)&1) & ((~R11)&1) & ((~R10)&1) & ((~R9)&1) & R8&R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if there was a carry from the MSB of the result; cleared otherwise.",
"op": "((~R15)&1) & Rdh7"
}
]
}
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "AND",
"description": "Performs the logical AND between the contents of register Rd and register Rr, and places the result in the destination\nregister Rd. Rd ← Rd ∧ Rr\nPC ← PC + 1",
"opcode": {
"base": "0010000000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rd ∧ Rr",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Cleared.",
"op": "0"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "ANDI",
"description": "Performs the logical AND between the contents of register Rd and a constant, and places the result in the destination\nregister Rd. Rd ← Rd ∧ K\nPC ← PC + 1",
"opcode": {
"base": "0111000000000000",
"mask": "1111000000000000"
},
"args": [
{
"name": "d",
"mask": "0000000011110000",
"limits": "16 ≤ d ≤ 31"
},
{
"name": "K",
"mask": "0000111100001111",
"limits": " 0 ≤ K ≤ 255"
}
],
"ops": [
" Rd ← Rd ∧ K",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Cleared.",
"op": "0"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "ASR",
"description": "Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C flag of the SREG. This\noperation effectively divides a signed value by two without changing its sign. The Carry flag can be used to round the\nresult.\nPC ← PC + 1",
"opcode": {
"base": "1001010000000101",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": " for N and C after the shift.",
"op": "N ^ C"
},
{
"flag": "N",
"description": null,
"op": "R7. Set if MSB of the result is set; cleared otherwise."
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if, before the shift, the LSB of Rd was set; cleared otherwise.",
"op": "Rd0"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "BCLR",
"description": "Clears a single flag in SREG. SREG(s) ← 0\nPC ← PC + 1",
"opcode": {
"base": "1001010010001000",
"mask": "1111111110001111"
},
"args": [
{
"name": "s",
"mask": "0000000001110000",
"limits": "0 ≤ s ≤ 7"
}
],
"ops": [
" SREG(s) ← 0",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "I",
"description": null,
"op": "0 if s = 7; Unchanged otherwise."
},
{
"flag": "T",
"description": null,
"op": "0 if s = 6; Unchanged otherwise."
},
{
"flag": "H",
"description": null,
"op": "0 if s = 5; Unchanged otherwise."
},
{
"flag": "S",
"description": null,
"op": "0 if s = 4; Unchanged otherwise."
},
{
"flag": "V",
"description": null,
"op": "0 if s = 3; Unchanged otherwise."
},
{
"flag": "N",
"description": null,
"op": "0 if s = 2; Unchanged otherwise."
},
{
"flag": "Z",
"description": null,
"op": "0 if s = 1; Unchanged otherwise."
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "BLD",
"description": "Copies the T bit in the SREG (Status Register) to bit b in register Rd. Rd(b) ← T\nPC ← PC + 1",
"opcode": {
"base": "1111100000000000",
"mask": "1111111000001000"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
},
{
"name": "b",
"mask": "0000000000000111",
"limits": " 0 ≤ b ≤ 7"
}
],
"ops": [
" Rd(b) ← T",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "BRBC",
"description": "Conditional relative branch. Tests a single bit in SREG and branches relatively to the PC if the bit is cleared. This\ninstruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset\nfrom the PC and is represented in two’s complement form. If SREG(s) == 0 then PC ← PC + k + 1, else PC ← PC + 1",
"opcode": {
"base": "1111010000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "k",
"mask": "0000001111111000"
},
{
"name": "s",
"mask": "0000000000000111"
}
],
"ops": [
" If SREG(s) == 0 then PC ← PC + k + 1, else PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "BRBS",
"description": "Conditional relative branch. Tests a single bit in SREG and branches relatively to the PC if the bit is set. This\ninstruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset\nfrom the PC and is represented in two’s complement form. If SREG(s) == 1 then PC ← PC + k + 1, else PC ← PC + 1",
"opcode": {
"base": "1111000000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "k",
"mask": "0000001111111000"
},
{
"name": "s",
"mask": "0000000000000111"
}
],
"ops": [
" If SREG(s) == 1 then PC ← PC + k + 1, else PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "BREAK",
"description": "The BREAK instruction is used by the On-chip Debug system and not used by the application software. When the\nBREAK instruction is executed, the AVR CPU is set in the Stopped state. This gives the On-chip Debugger access to\ninternal resources.\nIf the device is locked, or the on-chip debug system is not enabled, the CPU will treat the BREAK instruction as a\nNOP and will not enter the Stopped state.\nThis instruction is not available on all devices. Refer to Appendix A. On-chip Debug system breakpoint instruction.",
"opcode": {
"base": "1001010110011000",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" On-chip Debug system breakpoint instruction."
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "BSET",
"description": "Sets a single flag or bit in SREG. SREG(s) ← 1\nPC ← PC + 1",
"opcode": {
"base": "1001010000001000",
"mask": "1111111110001111"
},
"args": [
{
"name": "s",
"mask": "0000000001110000",
"limits": "0 ≤ s ≤ 7"
}
],
"ops": [
" SREG(s) ← 1",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "I",
"description": null,
"op": "1 if s = 7; Unchanged otherwise."
},
{
"flag": "T",
"description": null,
"op": "1 if s = 6; Unchanged otherwise."
},
{
"flag": "H",
"description": null,
"op": "1 if s = 5; Unchanged otherwise."
},
{
"flag": "S",
"description": null,
"op": "1 if s = 4; Unchanged otherwise."
},
{
"flag": "V",
"description": null,
"op": "1 if s = 3; Unchanged otherwise."
},
{
"flag": "N",
"description": null,
"op": "1 if s = 2; Unchanged otherwise."
},
{
"flag": "Z",
"description": null,
"op": "1 if s = 1; Unchanged otherwise."
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "BST",
"description": "Stores bit b from Rd to the T bit in SREG (Status Register). T ← Rd(b)\nPC ← PC + 1",
"opcode": {
"base": "1111101000000000",
"mask": "1111111000001000"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
},
{
"name": "b",
"mask": "0000000000000111",
"limits": " 0 ≤ b ≤ 7"
}
],
"ops": [
" T ← Rd(b)",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "CALL",
"description": "Calls to a subroutine within the entire program memory. The return address (to the instruction after the CALL) will be\nstored on the Stack. (See also RCALL.) The Stack Pointer uses a post-decrement scheme during CALL.\nThis instruction is not available on all devices. Refer to Appendix A. PC ← k Devices with 16-bit PC, 128 KB program memory maximum.\nPC ← k\nSTACK ← PC+2",
"opcode": {
"base": "10010100000011100000000000000000",
"mask": "11111110000011100000000000000000"
},
"args": [
{
"name": "k",
"mask": "00000001111100011111111111111111",
"limits": "0 ≤ k < 64K"
}
],
"ops": [
" PC ← k Devices with 16-bit PC, 128 KB program memory maximum.",
"PC ← k",
"STACK ← PC+2"
],
"cycle_selector": {
"AVRe": "4(1)",
"AVRxm": "3(1)",
"AVRxt": 3,
"AVRrc": "N/A"
},
"variant": "(i)"
},
{
"mnemonic": "CALL",
"description": "Calls to a subroutine within the entire program memory. The return address (to the instruction after the CALL) will be\nstored on the Stack. (See also RCALL.) The Stack Pointer uses a post-decrement scheme during CALL.\nThis instruction is not available on all devices. Refer to Appendix A. PC ← k Devices with 22-bit PC, 8 MB program memory maximum.",
"opcode": {
"base": "10010100000011100000000000000000",
"mask": "11111110000011100000000000000000"
},
"args": [
{
"name": "k",
"mask": "00000001111100011111111111111111"
}
],
"ops": [
" PC ← k Devices with 22-bit PC, 8 MB program memory maximum."
],
"cycle_selector": {
"AVRe": "4(1)",
"AVRxm": "3(1)",
"AVRxt": 3,
"AVRrc": "N/A"
},
"variant": "(ii)"
},
{
"mnemonic": "CBI",
"description": "Clears a specified bit in an I/O Register. This instruction operates on the lower 32 I/O Registers - addresses 0-31. I/O(A,b) ← 0\nPC ← PC + 1",
"opcode": {
"base": "1001100000000000",
"mask": "1111111100000000"
},
"args": [
{
"name": "b",
"mask": "0000000000000111",
"limits": " 0 ≤ b ≤ 7"
},
{
"name": "A",
"mask": "0000000011111000",
"limits": "0 ≤ A ≤ 31"
}
],
"ops": [
" I/O(A,b) ← 0",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "COM",
"description": "This instruction performs a One’s Complement of register Rd. Rd ← 0xFF - Rd\nPC ← PC + 1",
"opcode": {
"base": "1001010000000000",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← 0xFF - Rd",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Cleared.",
"op": "0"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set.",
"op": "1"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "CP",
"description": "This instruction performs a compare between two registers Rd and Rr. None of the registers are changed. All\nconditional branches can be used after this instruction. Rd - Rr\nPC ← PC + 1",
"opcode": {
"base": "0001010000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd - Rr",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a borrow from bit 3; cleared otherwise.",
"op": "((~Rd3)&1) & Rr3 | Rr3 & R3 | R3 & ((~Rd3)&1)"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & ((~Rr7)&1) & ((~R7)&1) | ((~Rd7)&1) & Rr7 & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.",
"op": "((~Rd7)&1) & Rr7 | Rr7 & R7 | R7 & ((~Rd7)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "CPC",
"description": "This instruction performs a compare between two registers Rd and Rr and also takes into account the previous carry.\nNone of the registers are changed. All conditional branches can be used after this instruction. Rd - Rr - C\nPC ← PC + 1",
"opcode": {
"base": "0000010000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd - Rr - C",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a borrow from bit 3; cleared otherwise.",
"op": "((~Rd3)&1) & Rr3 | Rr3 & R3 | R3 & ((~Rd3)&1)"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & ((~Rr7)&1) & ((~R7)&1) | ((~Rd7)&1) & Rr7 & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Previous value remains unchanged when the result is zero; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1) & Z"
},
{
"flag": "C",
"description": "Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of Rd; cleared",
"op": "((~Rd7)&1) & Rr7 | Rr7 & R7 | R7 & ((~Rd7)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "CPI",
"description": "This instruction performs a compare between register Rd and a constant. The register is not changed. All conditional\nbranches can be used after this instruction. Rd - K\nPC ← PC + 1",
"opcode": {
"base": "0011000000000000",
"mask": "1111000000000000"
},
"args": [
{
"name": "d",
"mask": "0000000011110000",
"limits": "16 ≤ d ≤ 31"
},
{
"name": "K",
"mask": "0000111100001111",
"limits": " 0 ≤ K ≤ 255"
}
],
"ops": [
" Rd - K",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a borrow from bit 3; cleared otherwise.",
"op": "((~Rd3)&1) & K3 | K3 & R3 | R3 & ((~Rd3)&1)"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & ((~K7)&1) & ((~R7)&1) | ((~Rd7)&1) & K7 & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.",
"op": "((~Rd7)&1) & K7 | K7 & R7 | R7 & ((~Rd7)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "CPSE",
"description": "This instruction performs a compare between two registers Rd and Rr and skips the next instruction if Rd == Rr. If Rd == Rr then PC ← PC + 2 (or 3) else PC ← PC + 1\nPC ← PC + 1, Condition false - no skip",
"opcode": {
"base": "0001000000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" If Rd == Rr then PC ← PC + 2 (or 3) else PC ← PC + 1",
"PC ← PC + 1, Condition false - no skip"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "DEC",
"description": "Subtracts one -1- from the contents of register Rd and places the result in the destination register Rd.\nThe C flag in SREG is not affected by the operation, thus allowing the DEC instruction to be used on a loop counter\nin multiple-precision computations.\nWhen operating on unsigned values, only BREQ and BRNE branches can be expected to perform consistently. When\noperating on two’s complement values, all signed branches are available. Rd ← Rd - 1\nPC ← PC + 1",
"opcode": {
"base": "1001010000001010",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rd - 1",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise. Two’s complement overflow",
"op": "((~R7)&1) & R6 & R5 & R4 & R3 & R2 & R1 & R0"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "DES",
"description": "The module is an instruction set extension to the AVR CPU, performing DES iterations. The 64-bit data block\n(plaintext or ciphertext) is placed in the CPU Register File, registers R0-R7, where the LSB of data is placed in the\nLSB of R0 and the MSB of data is placed in the MSB of R7. The full 64-bit key (including parity bits) is placed in\nregisters R8-R15, organized in the Register File with the LSB of the key in the LSB of R8 and the MSB of the key in\nthe MSB of R15. Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must be\nexecuted in increasing order to form the correct DES ciphertext or plaintext. Intermediate results are stored in the\nRegister File (R0-R15) after each DES instruction. The instruction's operand (K) determines which round is executed,\nand the Half Carry (H) flag determines whether encryption or decryption is performed.\nThe DES algorithm is described in “Specifications for the Data Encryption Standard” (Federal Information Processing\nStandards Publication 46). Intermediate results in this implementation differ from the standard because the initial\npermutation and the inverse initial permutation are performed in each iteration. This does not affect the result in the\nfinal ciphertext or plaintext but reduces the execution time. If H = 0 then Encrypt round (R7-R0, R15-R8, K)\nIf H = 1 then Decrypt round (R7-R0, R15-R8, K)",
"opcode": {
"base": "1001010000001011",
"mask": "1111111100001111"
},
"args": [
{
"name": "K",
"mask": "0000000011110000"
}
],
"ops": [
" If H = 0 then Encrypt round (R7-R0, R15-R8, K)",
"If H = 1 then Decrypt round (R7-R0, R15-R8, K)"
],
"cycle_selector": {
"AVRe": "N/A",
"AVRxm": 1,
"AVRxt": "N/A",
"AVRrc": "N/A"
}
},
{
"mnemonic": "EICALL",
"description": "Indirect call of a subroutine pointed to by the Z (16-bit) Pointer Register in the Register File and the EIND Register in\nthe I/O space. This instruction allows for indirect calls to the entire 4M (words) program memory space. See also\nICALL. The Stack Pointer uses a post-decrement scheme during EICALL.\nThis instruction is not available on all devices. Refer to Appendix A. PC(15:0) ← Z(15:0)\nPC(21:16) ← EIND",
"opcode": {
"base": "1001010100011001",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" PC(15:0) ← Z(15:0)",
"PC(21:16) ← EIND"
],
"cycle_selector": {
"AVRe": "4(2)",
"AVRxm": "3(2)",
"AVRxt": 3,
"AVRrc": "N/A"
}
},
{
"mnemonic": "EIJMP",
"description": "Indirect jump to the address pointed to by the Z (16-bit) Pointer Register in the Register File and the EIND Register in\nthe I/O space. This instruction allows for indirect jumps to the entire 4M (words) program memory space. See also\nIJMP.\nThis instruction is not available on all devices. Refer to Appendix A. PC(15:0) ← Z(15:0)\nPC(21:16) ← EIND",
"opcode": {
"base": "1001010000011001",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" PC(15:0) ← Z(15:0)",
"PC(21:16) ← EIND"
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "ELPM",
"description": "Loads one byte pointed to by the Z-register and the RAMPZ Register in the I/O space, and places this byte in the\ndestination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch.\nThe program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit\nof the Z-pointer selects either low byte (Z\nLSB\n = 0) or high byte (Z\nLSB\n = 1). This instruction can address the entire\nprogram memory space. The Z-Pointer Register can either be left unchanged by the operation, or it can be\nincremented. The incrementation applies to the entire 24-bit concatenation of the RAMPZ and Z-Pointer Registers.\nDevices with self-programming capability can use the ELPM instruction to read the Fuse and Lock bit value. Refer to\nthe device documentation for a detailed description.\nThis instruction is not available on all devices. Refer to Appendix A.\nThe result of these combinations is undefined:\nELPM r30, Z+\nELPM r31, Z+ R0 ← PS(RAMPZ:Z) RAMPZ:Z: Unchanged, R0\nimplied destination register",
"opcode": {
"base": "1001010111011000",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" R0 ← PS(RAMPZ:Z) RAMPZ:Z: Unchanged, R0",
"implied destination register"
],
"cycle_selector": {
"AVRe": 3,
"AVRxm": 3,
"AVRxt": 3,
"AVRrc": "N/A"
},
"variant": "(i)"
},
{
"mnemonic": "ELPM",
"description": "Loads one byte pointed to by the Z-register and the RAMPZ Register in the I/O space, and places this byte in the\ndestination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch.\nThe program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit\nof the Z-pointer selects either low byte (Z\nLSB\n = 0) or high byte (Z\nLSB\n = 1). This instruction can address the entire\nprogram memory space. The Z-Pointer Register can either be left unchanged by the operation, or it can be\nincremented. The incrementation applies to the entire 24-bit concatenation of the RAMPZ and Z-Pointer Registers.\nDevices with self-programming capability can use the ELPM instruction to read the Fuse and Lock bit value. Refer to\nthe device documentation for a detailed description.\nThis instruction is not available on all devices. Refer to Appendix A.\nThe result of these combinations is undefined:\nELPM r30, Z+\nELPM r31, Z+ Rd ← PS(RAMPZ:Z) RAMPZ:Z: Unchanged\nPC ← PC + 1",
"opcode": {
"base": "1001000000000110",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← PS(RAMPZ:Z) RAMPZ:Z: Unchanged",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 3,
"AVRxm": 3,
"AVRxt": 3,
"AVRrc": "N/A"
},
"variant": "(ii)"
},
{
"mnemonic": "ELPM",
"description": "Loads one byte pointed to by the Z-register and the RAMPZ Register in the I/O space, and places this byte in the\ndestination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch.\nThe program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit\nof the Z-pointer selects either low byte (Z\nLSB\n = 0) or high byte (Z\nLSB\n = 1). This instruction can address the entire\nprogram memory space. The Z-Pointer Register can either be left unchanged by the operation, or it can be\nincremented. The incrementation applies to the entire 24-bit concatenation of the RAMPZ and Z-Pointer Registers.\nDevices with self-programming capability can use the ELPM instruction to read the Fuse and Lock bit value. Refer to\nthe device documentation for a detailed description.\nThis instruction is not available on all devices. Refer to Appendix A.\nThe result of these combinations is undefined:\nELPM r30, Z+\nELPM r31, Z+ Rd ← PS(RAMPZ:Z) (RAMPZ:Z) ← (RAMPZ:Z)\n+ 1 RAMPZ:Z: Post\nincremented",
"opcode": {
"base": "1001000000000111",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000"
}
],
"ops": [
" Rd ← PS(RAMPZ:Z) (RAMPZ:Z) ← (RAMPZ:Z)",
"+ 1 RAMPZ:Z: Post",
"incremented"
],
"cycle_selector": {
"AVRe": 3,
"AVRxm": 3,
"AVRxt": 3,
"AVRrc": "N/A"
},
"variant": "(iii)"
},
{
"mnemonic": "EOR",
"description": "Performs the logical EOR between the contents of register Rd and register Rr and places the result in the destination\nregister Rd. Rd ← Rd ⊕ Rr\nPC ← PC + 1",
"opcode": {
"base": "0010010000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rd ⊕ Rr",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Cleared.",
"op": "0"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "FMUL",
"description": "This instruction performs 8-bit × 8-bit → 16-bit unsigned multiplication and shifts the result one bit left.\nRd Rr R1 R0\nMultiplicand × Multiplier → Product High Product Low\n8 8 16\nLet (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix\npoint. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).\n(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14)\nformat for the product. A left shift is required for the high byte of the product to be in the same format as the inputs.\nThe FMUL instruction incorporates the shift operation in the same number of cycles as MUL.\nThe (1.7) format is most commonly used with signed numbers, while FMUL performs an unsigned multiplication. This\ninstruction is, therefore, most useful for calculating one of the partial products when performing a signed multiplication\nwith 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format. R1:R0 ← Rd × Rr (unsigned (1.15) ← unsigned (1.7) × unsigned (1.7))\nPC ← PC + 1",
"opcode": {
"base": "0000001100001000",
"mask": "1111111110001000"
},
"args": [
{
"name": "r",
"mask": "0000000000000111",
"limits": " 16 ≤ r ≤ 23"
},
{
"name": "d",
"mask": "0000000001110000",
"limits": "16 ≤ d ≤ 23"
}
],
"ops": [
" R1:R0 ← Rd × Rr (unsigned (1.15) ← unsigned (1.7) × unsigned (1.7))",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "Z",
"description": "Set if the result is 0x0000; cleared otherwise.",
"op": "((~R15)&1) & ((~R14)&1) & ((~R13)&1) & ((~R12)&1) & ((~R11)&1) & ((~R10)&1) & ((~R9)&1) & R8&R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if bit 15 of the result before left shift is set; cleared otherwise.",
"op": "R16"
}
]
}
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "FMULS",
"description": "This instruction performs 8-bit × 8-bit → 16-bit signed multiplication and shifts the result one bit left.\nRd Rr R1 R0\nMultiplicand × Multiplier → Product High Product Low\n8 8 16\nLet (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix\npoint. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).\n(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14)\nformat for the product. A left shift is required for the high byte of the product to be in the same format as the inputs.\nThe FMULS instruction incorporates the shift operation in the same number of cycles as MULS.\nThe multiplicand Rd and the multiplier Rr are two registers containing signed fractional numbers where the implicit\nradix point lies between bit 6 and bit 7. The 16-bit signed fractional product with the implicit radix point between bit 14\nand bit 15 is placed in R1 (high byte) and R0 (low byte). R1:R0 ← Rd × Rr (signed (1.15) ← signed (1.7) × signed (1.7))\nPC ← PC + 1",
"opcode": {
"base": "0000001110000000",
"mask": "1111111110001000"
},
"args": [
{
"name": "r",
"mask": "0000000000000111",
"limits": " 16 ≤ r ≤ 23"
},
{
"name": "d",
"mask": "0000000001110000",
"limits": "16 ≤ d ≤ 23"
}
],
"ops": [
" R1:R0 ← Rd × Rr (signed (1.15) ← signed (1.7) × signed (1.7))",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "Z",
"description": "Set if the result is 0x0000; cleared otherwise.",
"op": "((~R15)&1) & ((~R14)&1) & ((~R13)&1) & ((~R12)&1) & ((~R11)&1) & ((~R10)&1) & ((~R9)&1) & R8&R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if bit 15 of the result before left shift is set; cleared otherwise.",
"op": "R16"
}
]
}
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "FMULSU",
"description": "This instruction performs 8-bit × 8-bit → 16-bit signed multiplication and shifts the result one bit left.\nRd Rr R1 R0\nMultiplicand × Multiplier → Product High Product Low\n8 8 16\nLet (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix\npoint. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).\n(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14)\nformat for the product. A left shift is required for the high byte of the product to be in the same format as the inputs.\nThe FMULSU instruction incorporates the shift operation in the same number of cycles as MULSU.\nThe (1.7) format is most commonly used with signed numbers, while FMULSU performs a multiplication with one\nunsigned and one signed input. This instruction is, therefore, most useful for calculating two of the partial products\nwhen performing a signed multiplication with 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format. R1:R0 ← Rd × Rr (signed (1.15) ← signed (1.7) × unsigned (1.7))\nPC ← PC + 1",
"opcode": {
"base": "0000001110001000",
"mask": "1111111110001000"
},
"args": [
{
"name": "r",
"mask": "0000000000000111",
"limits": " 16 ≤ r ≤ 23"
},
{
"name": "d",
"mask": "0000000001110000",
"limits": "16 ≤ d ≤ 23"
}
],
"ops": [
" R1:R0 ← Rd × Rr (signed (1.15) ← signed (1.7) × unsigned (1.7))",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "Z",
"description": "Set if the result is 0x0000; cleared otherwise.",
"op": "((~R15)&1) & ((~R14)&1) & ((~R13)&1) & ((~R12)&1) & ((~R11)&1) & ((~R10)&1) & ((~R9)&1) & R8&R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if bit 15 of the result before left shift is set; cleared otherwise.",
"op": "R16"
}
]
}
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "ICALL",
"description": "Indirect call of a subroutine pointed to by the Z (16-bit) Pointer Register in the Register File. The Z-Pointer Register is\n16 bits wide and allows a call to a subroutine within the lowest 64K words (128 KB) section in the program memory\nspace. The Stack Pointer uses a post-decrement scheme during ICALL.\nThis instruction is not available on all devices. Refer to Appendix A. PC(15:0) ← Z(15:0) Devices with 16-bit PC, 128 KB program memory maximum.",
"opcode": {
"base": "1001010100001001",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" PC(15:0) ← Z(15:0) Devices with 16-bit PC, 128 KB program memory maximum."
],
"cycle_selector": {
"AVRe": "3(1)",
"AVRxm": "2(1)",
"AVRxt": 2,
"AVRrc": 3
}
},
{
"mnemonic": "IJMP",
"description": "Indirect jump to the address pointed to by the Z (16-bit) Pointer Register in the Register File. The Z-Pointer Register\nis 16 bits wide and allows jump within the lowest 64K words (128 KB) section of program memory.\nThis instruction is not available on all devices. Refer to Appendix A. PC ← Z(15:0) Devices with 16-bit PC, 128 KB program memory maximum.",
"opcode": {
"base": "1001010000001001",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" PC ← Z(15:0) Devices with 16-bit PC, 128 KB program memory maximum."
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": 2
}
},
{
"mnemonic": "IN",
"description": "Loads data from the I/O space into register Rd in the Register File. Rd ← I/O(A)\nPC ← PC + 1",
"opcode": {
"base": "1011000000000000",
"mask": "1111100000000000"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
},
{
"name": "A",
"mask": "0000011000001111",
"limits": " 0 ≤ A ≤ 63"
}
],
"ops": [
" Rd ← I/O(A)",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "INC",
"description": "Adds one -1- to the contents of register Rd and places the result in the destination register Rd.\nThe C flag in SREG is not affected by the operation, thus allowing the INC instruction to be used on a loop counter in\nmultiple-precision computations.\nWhen operating on unsigned numbers, only BREQ and BRNE branches can be expected to perform consistently.\nWhen operating on two’s complement values, all signed branches are available. Rd ← Rd + 1\nPC ← PC + 1",
"opcode": {
"base": "1001010000000011",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rd + 1",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise. Two’s complement overflow",
"op": "R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "JMP",
"description": "Jump to an address within the entire 4M (words) program memory. See also RJMP.\nThis instruction is not available on all devices. Refer to Appendix A. PC ← k",
"opcode": {
"base": "10010100000011000000000000000000",
"mask": "11111110000011100000000000000000"
},
"args": [
{
"name": "k",
"mask": "00000001111100011111111111111111"
}
],
"ops": [
" PC ← k"
],
"cycle_selector": {
"AVRe": 3,
"AVRxm": 3,
"AVRxt": 3,
"AVRrc": "N/A"
}
},
{
"mnemonic": "LAC",
"description": "Load one byte indirect from data space to register and stores and clear the bits in data space specified by the\nregister. The instruction can only be used towards internal SRAM.\nThe data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPZ in the register in the I/O area has to be changed.\nThe Z-Pointer Register is left unchanged by the operation. This instruction is especially suited for clearing status bits\nstored in SRAM. DS(Z) ← (0xFF - Rd) ∧ DS(Z), Rd ← DS(Z)\nPC ← PC + 1",
"opcode": {
"base": "1001001000000110",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000"
}
],
"ops": [
" DS(Z) ← (0xFF - Rd) ∧ DS(Z), Rd ← DS(Z)",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "N/A",
"AVRxm": 2,
"AVRxt": "N/A",
"AVRrc": "N/A"
}
},
{
"mnemonic": "LAS",
"description": "Load one byte indirect from data space to register and set bits in the data space specified by the register. The\ninstruction can only be used towards internal SRAM.\nThe data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPZ in the register in the I/O area has to be changed.\nThe Z-Pointer Register is left unchanged by the operation. This instruction is especially suited for setting status bits\nstored in SRAM. DS(Z) ← Rd (v) DS(Z), Rd ← DS(Z)\nPC ← PC + 1",
"opcode": {
"base": "1001001000000101",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000"
}
],
"ops": [
" DS(Z) ← Rd (v) DS(Z), Rd ← DS(Z)",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "N/A",
"AVRxm": 2,
"AVRxt": "N/A",
"AVRrc": "N/A"
}
},
{
"mnemonic": "LAT",
"description": "Load one byte indirect from data space to register and toggles bits in the data space specified by the register. The\ninstruction can only be used towards SRAM.\nThe data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPZ in the register in the I/O area has to be changed.\nThe Z-Pointer Register is left unchanged by the operation. This instruction is especially suited for changing status bits\nstored in SRAM. DS(Z) ← Rd ⊕ DS(Z), Rd ← DS(Z)\nPC ← PC + 1",
"opcode": {
"base": "1001001000000111",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000"
}
],
"ops": [
" DS(Z) ← Rd ⊕ DS(Z), Rd ← DS(Z)",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "N/A",
"AVRxm": 2,
"AVRxt": "N/A",
"AVRrc": "N/A"
}
},
{
"mnemonic": "LD",
"description": "Loads one byte indirect from the data space to a register. The data space usually consists of the Register File, I/O\nmemory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the X (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPX in the register in the I/O area has to be changed.\nThe X-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the X-\nPointer Register. Note that only the low byte of the X-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPX Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/decrement is added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nIn the Reduced Core AVRrc, the LD instruction can be used to achieve the same operation as LPM since the\nprogram memory is mapped to the data memory space.\nThe result of these combinations is undefined:\nLD r26, X+\nLD r27, X+\nLD r26, -X\nLD r27, -X\nUsing the X-pointer: Rd ← DS(X) X: Unchanged\nPC ← PC + 1",
"opcode": {
"base": "1001000000001100",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← DS(X) X: Unchanged",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": "2(2)",
"AVRrc": 1
},
"variant": "(i)"
},
{
"mnemonic": "LD",
"description": "Loads one byte indirect from the data space to a register. The data space usually consists of the Register File, I/O\nmemory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the X (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPX in the register in the I/O area has to be changed.\nThe X-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the X-\nPointer Register. Note that only the low byte of the X-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPX Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/decrement is added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nIn the Reduced Core AVRrc, the LD instruction can be used to achieve the same operation as LPM since the\nprogram memory is mapped to the data memory space.\nThe result of these combinations is undefined:\nLD r26, X+\nLD r27, X+\nLD r26, -X\nLD r27, -X\nUsing the X-pointer: Rd ← DS(X) X ← X + 1 X: Post incremented",
"opcode": {
"base": "1001000000001101",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000"
}
],
"ops": [
" Rd ← DS(X) X ← X + 1 X: Post incremented"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": "2(2)",
"AVRrc": 1
},
"variant": "(ii)"
},
{
"mnemonic": "LD_LDD",
"description": "Loads one byte indirect with or without displacement from the data space to a register. The data space usually\nconsists of the Register File, I/O memory and SRAM, refer to the device data sheet for a detailed definition of the\ndata space.\nThe data location is pointed to by the Y (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPY in the register in the I/O area has to be changed.\nThe Y-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the Y-\nPointer Register. Note that only the low byte of the Y-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPY Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/decrement/displacement is added to the entire 24-bit address on such\ndevices.\nNot all variants of this instruction are available on all devices.\nIn the Reduced Core AVRrc, the LD instruction can be used to achieve the same operation as LPM since the\nprogram memory is mapped to the data memory space.\nThe result of these combinations is undefined:\nLD r28, Y+\nLD r29, Y+\nLD r28, -Y\nLD r29, -Y\nUsing the Y-pointer: Rd ← DS(Y), Y ← Y + 1 Y: Post incremented",
"opcode": {
"base": "1001000000001001",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000"
}
],
"ops": [
" Rd ← DS(Y), Y ← Y + 1 Y: Post incremented"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": 2,
"AVRrc": 1
},
"variant": "(ii)"
},
{
"mnemonic": "LD_LDD_1",
"description": "Loads one byte indirect with or without displacement from the data space to a register. The data space usually\nconsists of the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the\ndata space.\nThe data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPZ in the register in the I/O area has to be changed.\nThe Z-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for Stack Pointer usage of the Z-pointer Register. However,\nbecause the Z-Pointer Register can be used for indirect subroutine calls, indirect jumps, and table look-up, it is often\nmore convenient to use the X- or Y-pointer as a dedicated Stack Pointer. Note that only the low byte of the Z-pointer\nis updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not\nused by this instruction and can be used for other purposes. The RAMPZ Register in the I/O area is updated in parts\nwith more than 64 KB data space or more than 64 KB program memory, and the increment/decrement/displacement\nis added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nIn the Reduced Core AVRrc, the LD instruction can be used to achieve the same operation as LPM since the\nprogram memory is mapped to the data memory space.\nFor using the Z-pointer for table look-up in program memory, see the LPM and ELPM instructions.\nThe result of these combinations is undefined:\nLD r30, Z+\nLD r31, Z+\nLD r30, -Z\nLD r31, -Z\nUsing the Z-pointer: Rd ← DS(Z), Z ← Z + 1 Z: Post incremented",
"opcode": {
"base": "1001000000000001",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000"
}
],
"ops": [
" Rd ← DS(Z), Z ← Z + 1 Z: Post incremented"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": 2,
"AVRrc": 1
},
"variant": "(ii)"
},
{
"mnemonic": "LDI",
"description": "Loads an 8-bit constant directly to register 16 to 31. Rd ← K\nPC ← PC + 1",
"opcode": {
"base": "1110000000000000",
"mask": "1111000000000000"
},
"args": [
{
"name": "d",
"mask": "0000000011110000",
"limits": "16 ≤ d ≤ 31"
},
{
"name": "K",
"mask": "0000111100001111",
"limits": " 0 ≤ K ≤ 255"
}
],
"ops": [
" Rd ← K",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "LDS",
"description": "Loads one byte from the data space to a register. The data space usually consists of the Register File, I/O memory,\nand SRAM, refer to the device data sheet for a detailed definition of the data space.\nA 16-bit address must be supplied. Memory access is limited to the current data segment of 64 KB. The LDS\ninstruction uses the RAMPD Register to access memory above 64 KB. To access another data segment in devices\nwith more than 64 KB data space, the RAMPD in the register in the I/O area has to be changed.\nThis instruction is not available on all devices. Refer to Appendix A. Rd ← DS(k)\nPC ← PC + 2",
"opcode": {
"base": "10010000000000000000000000000000",
"mask": "11111110000011110000000000000000"
},
"args": [
{
"name": "k",
"mask": "00000000000000001111111111111111",
"limits": " 0 ≤ k ≤ 65535"
},
{
"name": "d",
"mask": "00000001111100000000000000000000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← DS(k)",
"PC ← PC + 2"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "3(1)(3)",
"AVRxt": "3(2)",
"AVRrc": "N/A"
}
},
{
"mnemonic": "LDS_AVRrc",
"description": "Loads one byte from the data space to a register. The data space usually consists of the Register File, I/O memory,\nand SRAM, refer to the device data sheet for a detailed definition of the data space.\nA 7-bit address must be supplied. The address given in the instruction is coded to a data space address as follows:\nADDR[7:0] = (INST[8], INST[8], INST[10], INST[9], INST[3], INST[2], INST[1], INST[0])\nMemory access is limited to the address range 0x40...0xbf.\nThis instruction is not available on all devices. Refer to Appendix A. Rd ← (k)\nPC ← PC + 1",
"opcode": {
"base": "1010000000000000",
"mask": "1111100000000000"
},
"args": [
{
"name": "k",
"mask": "0000011100001111",
"limits": " 0 ≤ k ≤ 127"
},
{
"name": "d",
"mask": "0000000011110000",
"limits": "16 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← (k)",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "N/A",
"AVRxm": "N/A",
"AVRxt": "N/A",
"AVRrc": 2
}
},
{
"mnemonic": "LPM",
"description": "Loads one byte pointed to by the Z-register into the destination register Rd. This instruction features a 100% space-\neffective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-\npointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (Z\nLSb\n = 0) or high byte\n(Z\nLSb\n = 1). This instruction can address the first 64 KB (32K words) of program memory. The Z-Pointer Register can\neither be left unchanged by the operation, or it can be incremented. The incrementation does not apply to the RAMPZ\nRegister.\nDevices with self-programming capability can use the LPM instruction to read the Fuse and Lock bit values. Refer to\nthe device documentation for a detailed description.\nThe LPM instruction is not available on all devices. Refer to Appendix A.\nThe result of these combinations is undefined:\nLPM r30, Z+\nLPM r31, Z+ R0 ← PS(Z) Z: Unchanged, R0 implied\ndestination register",
"opcode": {
"base": "1001010111001000",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" R0 ← PS(Z) Z: Unchanged, R0 implied",
"destination register"
],
"cycle_selector": {
"AVRe": 3,
"AVRxm": 3,
"AVRxt": 3,
"AVRrc": "N/A"
},
"variant": "(i)"
},
{
"mnemonic": "LPM",
"description": "Loads one byte pointed to by the Z-register into the destination register Rd. This instruction features a 100% space-\neffective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-\npointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (Z\nLSb\n = 0) or high byte\n(Z\nLSb\n = 1). This instruction can address the first 64 KB (32K words) of program memory. The Z-Pointer Register can\neither be left unchanged by the operation, or it can be incremented. The incrementation does not apply to the RAMPZ\nRegister.\nDevices with self-programming capability can use the LPM instruction to read the Fuse and Lock bit values. Refer to\nthe device documentation for a detailed description.\nThe LPM instruction is not available on all devices. Refer to Appendix A.\nThe result of these combinations is undefined:\nLPM r30, Z+\nLPM r31, Z+ Rd ← PS(Z) Z: Unchanged\nPC ← PC + 1",
"opcode": {
"base": "1001000000000100",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← PS(Z) Z: Unchanged",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 3,
"AVRxm": 3,
"AVRxt": 3,
"AVRrc": "N/A"
},
"variant": "(ii)"
},
{
"mnemonic": "LPM",
"description": "Loads one byte pointed to by the Z-register into the destination register Rd. This instruction features a 100% space-\neffective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-\npointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (Z\nLSb\n = 0) or high byte\n(Z\nLSb\n = 1). This instruction can address the first 64 KB (32K words) of program memory. The Z-Pointer Register can\neither be left unchanged by the operation, or it can be incremented. The incrementation does not apply to the RAMPZ\nRegister.\nDevices with self-programming capability can use the LPM instruction to read the Fuse and Lock bit values. Refer to\nthe device documentation for a detailed description.\nThe LPM instruction is not available on all devices. Refer to Appendix A.\nThe result of these combinations is undefined:\nLPM r30, Z+\nLPM r31, Z+ Rd ← PS(Z) Z ← Z + 1 Z: Post incremented",
"opcode": {
"base": "1001000000000101",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000"
}
],
"ops": [
" Rd ← PS(Z) Z ← Z + 1 Z: Post incremented"
],
"cycle_selector": {
"AVRe": 3,
"AVRxm": 3,
"AVRxt": 3,
"AVRrc": "N/A"
},
"variant": "(iii)"
},
{
"mnemonic": "LSR",
"description": "Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is loaded into the C flag of the SREG. This operation\neffectively divides an unsigned value by two. The C flag can be used to round the result.\n→\n0 → b7 - - - - - - - - - - - - - - - - - - b0 → C\nPC ← PC + 1",
"opcode": {
"base": "1001010000000110",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
"→",
"0 → b7 - - - - - - - - - - - - - - - - - - b0 → C",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": " for N and C after the shift.",
"op": "N ^ C"
},
{
"flag": "N",
"description": null,
"op": "0"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if, before the shift, the LSB of Rd was set; cleared otherwise.",
"op": "Rd0"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "MOV",
"description": "This instruction makes a copy of one register into another. The source register Rr is left unchanged, while the\ndestination register Rd is loaded with a copy of Rr. Rd ← Rr\nPC ← PC + 1",
"opcode": {
"base": "0010110000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rr",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "MOVW",
"description": "This instruction makes a copy of one register pair into another register pair. The source register pair Rr+1:Rr is left\nunchanged, while the destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr.\nThis instruction is not available on all devices. Refer to Appendix A. R[d+1]:Rd ← R[r+1]:Rr\nPC ← PC + 1",
"opcode": {
"base": "0000000100000000",
"mask": "1111111100000000"
},
"args": [
{
"name": "r",
"mask": "0000000000001111",
"limits": " r ∈ {0,2"
},
{
"name": "d",
"mask": "0000000011110000",
"limits": "d ∈ {0,2"
}
],
"ops": [
" R[d+1]:Rd ← R[r+1]:Rr",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": "N/A"
}
},
{
"mnemonic": "MUL",
"description": "This instruction performs 8-bit × 8-bit → 16-bit unsigned multiplication.\nRd Rr R1 R0\nMultiplicand × Multiplier → Product High Product Low\n8 8 16\nThe multiplicand Rd and the multiplier Rr are two registers containing unsigned numbers. The 16-bit unsigned\nproduct is placed in R1 (high byte) and R0 (low byte). Note that if the multiplicand or the multiplier is selected from R0\nor R1, the result will overwrite those after multiplication.\nThis instruction is not available on all devices. Refer to Appendix A. R1:R0 ← Rd × Rr (unsigned ← unsigned × unsigned)\nPC ← PC + 1",
"opcode": {
"base": "1001110000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" R1:R0 ← Rd × Rr (unsigned ← unsigned × unsigned)",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "Z",
"description": "Set if the result is 0x0000; cleared otherwise.",
"op": "((~R15)&1) & ((~R14)&1) & ((~R13)&1) & ((~R12)&1) & ((~R11)&1) & ((~R10)&1) & ((~R9)&1) & R8&R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": null,
"op": "R15"
}
]
}
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "MULS",
"description": "This instruction performs 8-bit × 8-bit → 16-bit signed multiplication.\nRd Rr R1 R0\nMultiplicand × Multiplier → Product High Product Low\n8 8 16\nThe multiplicand Rd and the multiplier Rr are two registers containing signed numbers. The 16-bit signed product is\nplaced in R1 (high byte) and R0 (low byte).\nThis instruction is not available on all devices. Refer to Appendix A. R1:R0 ← Rd × Rr (signed ← signed × signed)\nPC ← PC + 1",
"opcode": {
"base": "0000001000000000",
"mask": "1111111100000000"
},
"args": [
{
"name": "r",
"mask": "0000000000001111",
"limits": " 16 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000011110000",
"limits": "16 ≤ d ≤ 31"
}
],
"ops": [
" R1:R0 ← Rd × Rr (signed ← signed × signed)",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "Z",
"description": "Set if the result is 0x0000; cleared otherwise.",
"op": "((~R15)&1) & ((~R14)&1) & ((~R13)&1) & ((~R12)&1) & ((~R11)&1) & ((~R10)&1) & ((~R9)&1) & R8&R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": null,
"op": "R15"
}
]
}
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "MULSU",
"description": "This instruction performs 8-bit × 8-bit → 16-bit multiplication of a signed and an unsigned number.\nRd Rr R1 R0\nMultiplicand Multiplier → Product High Product Low\n8 8 16\nThe multiplicand Rd and the multiplier Rr are two registers. The multiplicand Rd is a signed number, and the\nmultiplier Rr is unsigned. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).\nThis instruction is not available on all devices. Refer to Appendix A. R1:R0 ← Rd × Rr (signed ← signed × unsigned)\nPC ← PC + 1",
"opcode": {
"base": "0000001100000000",
"mask": "1111111110001000"
},
"args": [
{
"name": "r",
"mask": "0000000000000111",
"limits": " 16 ≤ r ≤ 23"
},
{
"name": "d",
"mask": "0000000001110000",
"limits": "16 ≤ d ≤ 23"
}
],
"ops": [
" R1:R0 ← Rd × Rr (signed ← signed × unsigned)",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "Z",
"description": "Set if the result is 0x0000; cleared otherwise.",
"op": "((~R15)&1) & ((~R14)&1) & ((~R13)&1) & ((~R12)&1) & ((~R11)&1) & ((~R10)&1) & ((~R9)&1) & R8&R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": null,
"op": "R15"
}
]
}
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "NEG",
"description": "Replaces the contents of register Rd with its two’s complement; the value 0x80 is left unchanged. Rd ← 0x00 - Rd\nPC ← PC + 1",
"opcode": {
"base": "1001010000000001",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← 0x00 - Rd",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a borrow from bit 3; cleared otherwise.",
"op": "R3 | Rd3"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if there is a two’s complement overflow from the implied subtraction from zero; cleared otherwise. A two’s",
"op": "R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if there is a borrow in the implied subtraction from zero; cleared otherwise. The C flag will be set in all cases",
"op": "R7 | R6 | R5 | R4 | R3 | R2 | R1 | R0"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "NOP",
"description": "This instruction performs a single cycle No Operation. No",
"opcode": {
"base": "0000000000000000",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" No"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "OR",
"description": "Performs the logical OR between the contents of register Rd and register Rr, and places the result in the destination\nregister Rd. Rd ← Rd v Rr\nPC ← PC + 1",
"opcode": {
"base": "0010100000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rd v Rr",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Cleared.",
"op": "0"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "OUT",
"description": "Stores data from register Rr in the Register File to I/O space. I/O(A) ← Rr\nPC ← PC + 1",
"opcode": {
"base": "1011100000000000",
"mask": "1111100000000000"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
},
{
"name": "A",
"mask": "0000011000001111",
"limits": " 0 ≤ A ≤ 63"
}
],
"ops": [
" I/O(A) ← Rr",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "POP",
"description": "This instruction loads register Rd with a byte from the STACK. The Stack Pointer is pre-incremented by 1 before the\nPOP.\nThis instruction is not available on all devices. Refer to Appendix A. Rd ← STACK\nPC ← PC + 1\nSP ← SP + 1",
"opcode": {
"base": "1001000000001111",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← STACK",
"PC ← PC + 1",
"SP ← SP + 1"
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": "2(1)",
"AVRxt": 2,
"AVRrc": 3
}
},
{
"mnemonic": "PUSH",
"description": "This instruction stores the contents of register Rr on the STACK. The Stack Pointer is post-decremented by 1 after\nthe PUSH.\nThis instruction is not available on all devices. Refer to Appendix A. STACK ← Rr\nPC ← PC + 1\nSP ← SP - 1",
"opcode": {
"base": "1001001000001111",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000"
}
],
"ops": [
" STACK ← Rr",
"PC ← PC + 1",
"SP ← SP - 1"
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": "1(1)",
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "RCALL",
"description": "Relative call to an address within PC - 2K + 1 and PC + 2K (words). The return address (the instruction after the\nRCALL) is stored onto the Stack. See also CALL. For AVR microcontrollers with program memory not exceeding 4K\nwords (8 KB), this instruction can address the entire memory from every address location. The Stack Pointer uses a\npost-decrement scheme during RCALL. PC ← PC + k + 1 Devices with 16-bit PC, 128 KB program memory maximum.\nPC ← PC + k + 1\nSTACK ← PC + 1",
"opcode": {
"base": "1101000000000000",
"mask": "1111000000000000"
},
"args": [
{
"name": "k",
"mask": "0000111111111111",
"limits": "-2K ≤ k < 2K"
}
],
"ops": [
" PC ← PC + k + 1 Devices with 16-bit PC, 128 KB program memory maximum.",
"PC ← PC + k + 1",
"STACK ← PC + 1"
],
"cycle_selector": {
"AVRe": "3(1)",
"AVRxm": "2(1)",
"AVRxt": 2,
"AVRrc": 3
}
},
{
"mnemonic": "RET",
"description": "Returns from the subroutine. The return address is loaded from the STACK. The Stack Pointer uses a pre-increment\nscheme during RET. PC(15:0) ← STACK Devices with 16-bit PC, 128 KB program memory maximum.",
"opcode": {
"base": "1001010100001000",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" PC(15:0) ← STACK Devices with 16-bit PC, 128 KB program memory maximum."
],
"cycle_selector": {
"AVRe": "4(1)",
"AVRxm": "4(1)",
"AVRxt": 4,
"AVRrc": 6
}
},
{
"mnemonic": "RETI",
"description": "Returns from the interrupt. The return address is loaded from the STACK, and the Global Interrupt Enable bit is set.\nNote that the Status Register is not automatically stored when entering an interrupt routine, and it is not restored\nwhen returning from an interrupt routine. This must be handled by the application program. The Stack Pointer uses a\npre-increment scheme during RETI. PC(15:0) ← STACK Devices with 16-bit PC, 128 KB program memory maximum.",
"opcode": {
"base": "1001010100011000",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" PC(15:0) ← STACK Devices with 16-bit PC, 128 KB program memory maximum.",
{
"sreg": [
{
"flag": "I",
"description": "The I flag is set.",
"op": "1"
}
]
}
],
"cycle_selector": {
"AVRe": "4(2)",
"AVRxm": "4(2)",
"AVRxt": 4,
"AVRrc": 6
}
},
{
"mnemonic": "RJMP",
"description": "Relative jump to an address within PC - 2K +1 and PC + 2K (words). For AVR microcontrollers with pogram memory\nnot exceeding 4K words (8 KB), this instruction can address the entire memory from every address location. See also\nJMP. PC ← PC + k + 1\nPC ← PC + k + 1\nUnchanged",
"opcode": {
"base": "1100000000000000",
"mask": "1111000000000000"
},
"args": [
{
"name": "k",
"mask": "0000111111111111",
"limits": "-2K ≤ k < 2K"
}
],
"ops": [
" PC ← PC + k + 1",
"PC ← PC + k + 1",
"Unchanged"
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": 2
}
},
{
"mnemonic": "ROR",
"description": "Shifts all bits in Rd one place to the right. The C flag is shifted into bit 7 of Rd. Bit 0 is shifted into the C flag. This\noperation, combined with ASR, effectively divides multi-byte signed values by two. Combined with LSR, it effectively\ndivides multi-byte unsigned values by two. The Carry flag can be used to round the result.PC ← PC + 1",
"opcode": {
"base": "1001010000000111",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": " for N and C after the shift.",
"op": "N ^ C"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if, before the shift, the LSB of Rd was set; cleared otherwise.",
"op": "Rd0"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SBC",
"description": "Subtracts two registers and subtracts with the C flag, and places the result in the destination register Rd. Rd ← Rd - Rr - C\nPC ← PC + 1",
"opcode": {
"base": "0000100000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rd - Rr - C",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a borrow from bit 3; cleared otherwise.",
"op": "((~Rd3)&1) & Rr3 | Rr3 & R3 | R3 & ((~Rd3)&1)"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & ((~Rr7)&1) & ((~R7)&1) | ((~Rd7)&1) & Rr7 & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Previous value remains unchanged when the result is zero; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1) & Z"
},
{
"flag": "C",
"description": "Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of the Rd;",
"op": "((~Rd7)&1) & Rr7 | Rr7 & R7 | R7 & ((~Rd7)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SBCI",
"description": "Subtracts a constant from a register and subtracts with the C flag, and places the result in the destination register Rd. Rd ← Rd - K - C\nPC ← PC + 1",
"opcode": {
"base": "0100000000000000",
"mask": "1111000000000000"
},
"args": [
{
"name": "d",
"mask": "0000000011110000",
"limits": "16 ≤ d ≤ 31"
},
{
"name": "K",
"mask": "0000111100001111",
"limits": " 0 ≤ K ≤ 255"
}
],
"ops": [
" Rd ← Rd - K - C",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a borrow from bit 3; cleared otherwise.",
"op": "((~Rd3)&1) & K3 | K3 & R3 | R3 & ((~Rd3)&1)"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & ((~K7)&1) & ((~R7)&1) | ((~Rd7)&1) & K7 & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Previous value remains unchanged when the result is zero; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1) & Z"
},
{
"flag": "C",
"description": "Set if the absolute value of the constant plus previous carry is larger than the absolute value of Rd; cleared",
"op": "((~Rd7)&1) & K7 | K7 & R7 | R7 & ((~Rd7)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SBI",
"description": "Sets a specified bit in an I/O Register. This instruction operates on the lower 32 I/O Registers - addresses 0-31. I/O(A,b) ← 1\nPC ← PC + 1",
"opcode": {
"base": "1001101000000000",
"mask": "1111111100000000"
},
"args": [
{
"name": "b",
"mask": "0000000000000111",
"limits": " 0 ≤ b ≤ 7"
},
{
"name": "A",
"mask": "0000000011111000",
"limits": "0 ≤ A ≤ 31"
}
],
"ops": [
" I/O(A,b) ← 1",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SBIC",
"description": "This instruction tests a single bit in an I/O Register and skips the next instruction if the bit is cleared. This instruction\noperates on the lower 32 I/O Registers - addresses 0-31. If I/O(A,b) == 0 then PC ← PC + 2 (or 3) else PC ← PC + 1\nPC ← PC + 1, Condition false - no skip",
"opcode": {
"base": "1001100100000000",
"mask": "1111111100000000"
},
"args": [
{
"name": "b",
"mask": "0000000000000111",
"limits": " 0 ≤ b ≤ 7"
},
{
"name": "A",
"mask": "0000000011111000",
"limits": "0 ≤ A ≤ 31"
}
],
"ops": [
" If I/O(A,b) == 0 then PC ← PC + 2 (or 3) else PC ← PC + 1",
"PC ← PC + 1, Condition false - no skip"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 2,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SBIS",
"description": "This instruction tests a single bit in an I/O Register and skips the next instruction if the bit is set. This instruction\noperates on the lower 32 I/O Registers - addresses 0-31. If I/O(A,b) == 1 then PC ← PC + 2 (or 3) else PC ← PC + 1\nPC ← PC + 1, Condition false - no skip",
"opcode": {
"base": "1001101100000000",
"mask": "1111111100000000"
},
"args": [
{
"name": "b",
"mask": "0000000000000111",
"limits": " 0 ≤ b ≤ 7"
},
{
"name": "A",
"mask": "0000000011111000",
"limits": "0 ≤ A ≤ 31"
}
],
"ops": [
" If I/O(A,b) == 1 then PC ← PC + 2 (or 3) else PC ← PC + 1",
"PC ← PC + 1, Condition false - no skip"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 2,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SBIW",
"description": "Subtracts an immediate value (0-63) from a register pair and places the result in the register pair. This instruction\noperates on the upper four register pairs and is well suited for operations on the Pointer Registers.\nThis instruction is not available on all devices. Refer to Appendix A. R[d+1]:Rd ← R[d+1]:Rd - K\nPC ← PC + 1",
"opcode": {
"base": "1001011100000000",
"mask": "1111111100000000"
},
"args": [
{
"name": "d",
"mask": "0000000000110000",
"limits": "d ∈ {24,26,28,30}"
},
{
"name": "K",
"mask": "0000000011001111",
"limits": " 0 ≤ K ≤ 63"
}
],
"ops": [
" R[d+1]:Rd ← R[d+1]:Rd - K",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "((~R15)&1) & Rdh7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R15"
},
{
"flag": "Z",
"description": "Set if the result is 0x0000; cleared otherwise.",
"op": "((~R15)&1) & ((~R14)&1) & ((~R13)&1) & ((~R12)&1) & ((~R11)&1) & ((~R10)&1) & ((~R9)&1) & R8&R7 & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.",
"op": "R15 & ((~Rdh7)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "SBR",
"description": "Sets specified bits in register Rd. Performs the logical ORI between the contents of register Rd and a constant mask\nK, and places the result in the destination register Rd. (Equivalent to ORI Rd,K.) Rd ← Rd v K\nPC ← PC + 1",
"opcode": {
"base": "0110000000000000",
"mask": "1111000000000000"
},
"args": [
{
"name": "d",
"mask": "0000000011110000",
"limits": "16 ≤ d ≤ 31"
},
{
"name": "K",
"mask": "0000111100001111",
"limits": " 0 ≤ K ≤ 255"
}
],
"ops": [
" Rd ← Rd v K",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Cleared.",
"op": "0"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SBRC",
"description": "This instruction tests a single bit in a register and skips the next instruction if the bit is cleared. If Rr(b) == 0 then PC ← PC + 2 (or 3) else PC ← PC + 1\nPC ← PC + 1, Condition false - no skip",
"opcode": {
"base": "1111110000000000",
"mask": "1111111000001000"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
},
{
"name": "b",
"mask": "0000000000000111",
"limits": " 0 ≤ b ≤ 7"
}
],
"ops": [
" If Rr(b) == 0 then PC ← PC + 2 (or 3) else PC ← PC + 1",
"PC ← PC + 1, Condition false - no skip"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SBRS",
"description": "This instruction tests a single bit in a register and skips the next instruction if the bit is set. If Rr(b) == 1 then PC ← PC + 2 (or 3) else PC ← PC + 1\nPC ← PC + 1, Condition false - no skip",
"opcode": {
"base": "1111111000000000",
"mask": "1111111000001000"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
},
{
"name": "b",
"mask": "0000000000000111",
"limits": " 0 ≤ b ≤ 7"
}
],
"ops": [
" If Rr(b) == 1 then PC ← PC + 2 (or 3) else PC ← PC + 1",
"PC ← PC + 1, Condition false - no skip"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SPM",
"description": "SPM can be used to erase a page in the program memory, to write a page in the program memory (that is already\nerased), and to set Boot Loader Lock bits. In some devices, the Program memory can be written one word at a time.\nIn other devices, an entire page can be programmed simultaneously after first filling a temporary page buffer. In all\ncases, the program memory must be erased one page at a time. When erasing the program memory, the RAMPZ\nand Z-register are used as page address. When writing the program memory, the RAMPZ and Z-register are used as\npage or word address, and the R1:R0 register pair is used as data(1). The Flash is word-accessed for code space\nwrite operations, so the least significant bit of the RAMPZ register concatenated with the Z register should be set to\n‘0’. When setting the Boot Loader Lock bits, the R1:R0 register pair is used as data. Refer to the device\ndocumentation for the detailed description of SPM usage. This instruction can address the entire program memory.\nThe SPM instruction is not available on all devices. Refer to Appendix A. PS(RAMPZ:Z) ← 0xffff Erase program memory page",
"opcode": {
"base": "1001010111101000",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" PS(RAMPZ:Z) ← 0xffff Erase program memory page"
],
"cycle_selector": {
"AVRe": "-(1)",
"AVRxm": "N/A",
"AVRxt": "N/A",
"AVRrc": "N/A"
}
},
{
"mnemonic": "ST",
"description": "Stores one byte indirect from a register to data space. The data space usually consists of the Register File, I/O\nmemory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the X (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPX in the register in the I/O area has to be changed.\nThe X-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the X-\nPointer Register. Note that only the low byte of the X-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPX Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/ decrement is added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST X+, r26\nST X+, r27\nST -X, r26\nST -X, r27\nUsing the X-pointer: DS(X) ← Rr X: Unchanged\nPC ← PC + 1",
"opcode": {
"base": "1001001000001100",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
}
],
"ops": [
" DS(X) ← Rr X: Unchanged",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "1(1)",
"AVRxt": "1(2)",
"AVRrc": 1
},
"variant": "(i)"
},
{
"mnemonic": "ST",
"description": "Stores one byte indirect from a register to data space. The data space usually consists of the Register File, I/O\nmemory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the X (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPX in the register in the I/O area has to be changed.\nThe X-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the X-\nPointer Register. Note that only the low byte of the X-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPX Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/ decrement is added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST X+, r26\nST X+, r27\nST -X, r26\nST -X, r27\nUsing the X-pointer: DS(X) ← Rr, X ← X+1 X: Post incremented\nPC ← PC + 1",
"opcode": {
"base": "1001001000001101",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
}
],
"ops": [
" DS(X) ← Rr, X ← X+1 X: Post incremented",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "1(1)",
"AVRxt": "1(2)",
"AVRrc": 1
},
"variant": "(ii)"
},
{
"mnemonic": "ST",
"description": "Stores one byte indirect from a register to data space. The data space usually consists of the Register File, I/O\nmemory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the X (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPX in the register in the I/O area has to be changed.\nThe X-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the X-\nPointer Register. Note that only the low byte of the X-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPX Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/ decrement is added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST X+, r26\nST X+, r27\nST -X, r26\nST -X, r27\nUsing the X-pointer: X ← X - 1, DS(X) ← Rr X: Pre decremented\nPC ← PC + 1",
"opcode": {
"base": "1001001000001110",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
}
],
"ops": [
" X ← X - 1, DS(X) ← Rr X: Pre decremented",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": "1(2)",
"AVRrc": 2
},
"variant": "(iii)"
},
{
"mnemonic": "ST_STD",
"description": "Stores one byte indirect with or without displacement from a register to data space. The data space usually consists\nof the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the Y (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPY in the register in the I/O area has to be changed.\nThe Y-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the Y-\nPointer Register. Note that only the low byte of the Y-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPY Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/ decrement/displacement is added to the entire 24-bit address on such\ndevices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST Y+, r28\nST Y+, r29\nST -Y, r28\nST -Y, r29\nUsing the Y-pointer: DS(Y) ← Rr, Y ← Y+1 Y: Post incremented\nPC ← PC + 1",
"opcode": {
"base": "1001001000001001",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
}
],
"ops": [
" DS(Y) ← Rr, Y ← Y+1 Y: Post incremented",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "1(1)",
"AVRxt": "1(2)",
"AVRrc": 1
},
"variant": "(ii)"
},
{
"mnemonic": "ST_STD",
"description": "Stores one byte indirect with or without displacement from a register to data space. The data space usually consists\nof the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the Y (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPY in the register in the I/O area has to be changed.\nThe Y-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the Y-\nPointer Register. Note that only the low byte of the Y-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPY Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/ decrement/displacement is added to the entire 24-bit address on such\ndevices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST Y+, r28\nST Y+, r29\nST -Y, r28\nST -Y, r29\nUsing the Y-pointer: Y ← Y - 1, DS(Y) ← Rr Y: Pre decremented\nPC ← PC + 1",
"opcode": {
"base": "1001001000001010",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
}
],
"ops": [
" Y ← Y - 1, DS(Y) ← Rr Y: Pre decremented",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": "1(2)",
"AVRrc": 2
},
"variant": "(iii)"
},
{
"mnemonic": "ST_STD",
"description": "Stores one byte indirect with or without displacement from a register to data space. The data space usually consists\nof the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the Y (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPY in the register in the I/O area has to be changed.\nThe Y-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the Y-\nPointer Register. Note that only the low byte of the Y-pointer is updated in devices with no more than 256 bytes of\ndata space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other\npurposes. The RAMPY Register in the I/O area is updated in parts with more than 64 KB data space or more than 64\nKB program memory, and the increment/ decrement/displacement is added to the entire 24-bit address on such\ndevices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST Y+, r28\nST Y+, r29\nST -Y, r28\nST -Y, r29\nUsing the Y-pointer: DS(Y+q) ← Rr Y: Unchanged, q:\nDisplacement\nPC ← PC + 1",
"opcode": {
"base": "1000001000001000",
"mask": "1101001000001000"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
},
{
"name": "q",
"mask": "0010110000000111",
"limits": " 0 ≤ q ≤ 63"
}
],
"ops": [
" DS(Y+q) ← Rr Y: Unchanged, q:",
"Displacement",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": "1(2)",
"AVRrc": "N/A"
},
"variant": "(iv)"
},
{
"mnemonic": "ST_STD_1",
"description": "Stores one byte indirect with or without displacement from a register to data space. The data space usually consists\nof the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPZ in the register in the I/O area has to be changed.\nThe Z-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for Stack Pointer usage of the Z-Pointer Register. However,\nbecause the Z-Pointer Register can be used for indirect subroutine calls, indirect jumps, and table look-up, it is often\nmore convenient to use the X- or Y-pointer as a dedicated Stack Pointer. Note that only the low byte of the Z-pointer\nis updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not\nused by this instruction and can be used for other purposes. The RAMPZ Register in the I/O area is updated in parts\nwith more than 64 KB data space or more than 64 KB program memory, and the increment/decrement/displacement\nis added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST Z+, r30\nST Z+, r31\nST -Z, r30\nST -Z, r31\nUsing the Z-pointer: DS(Z) ← Rr, Z ← Z+1 Z: Post incremented\nPC ← PC + 1",
"opcode": {
"base": "1001001000000001",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
}
],
"ops": [
" DS(Z) ← Rr, Z ← Z+1 Z: Post incremented",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "1(1)",
"AVRxt": "1(2)",
"AVRrc": 1
},
"variant": "(ii)"
},
{
"mnemonic": "ST_STD_1",
"description": "Stores one byte indirect with or without displacement from a register to data space. The data space usually consists\nof the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPZ in the register in the I/O area has to be changed.\nThe Z-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for Stack Pointer usage of the Z-Pointer Register. However,\nbecause the Z-Pointer Register can be used for indirect subroutine calls, indirect jumps, and table look-up, it is often\nmore convenient to use the X- or Y-pointer as a dedicated Stack Pointer. Note that only the low byte of the Z-pointer\nis updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not\nused by this instruction and can be used for other purposes. The RAMPZ Register in the I/O area is updated in parts\nwith more than 64 KB data space or more than 64 KB program memory, and the increment/decrement/displacement\nis added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST Z+, r30\nST Z+, r31\nST -Z, r30\nST -Z, r31\nUsing the Z-pointer: Z ← Z - 1, DS(Z) ← Rr Z: Pre decremented\nPC ← PC + 1",
"opcode": {
"base": "1001001000000010",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
}
],
"ops": [
" Z ← Z - 1, DS(Z) ← Rr Z: Pre decremented",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": "1(2)",
"AVRrc": 2
},
"variant": "(iii)"
},
{
"mnemonic": "ST_STD_1",
"description": "Stores one byte indirect with or without displacement from a register to data space. The data space usually consists\nof the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.\nThe data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPZ in the register in the I/O area has to be changed.\nThe Z-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre-\ndecremented. These features are especially suited for Stack Pointer usage of the Z-Pointer Register. However,\nbecause the Z-Pointer Register can be used for indirect subroutine calls, indirect jumps, and table look-up, it is often\nmore convenient to use the X- or Y-pointer as a dedicated Stack Pointer. Note that only the low byte of the Z-pointer\nis updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not\nused by this instruction and can be used for other purposes. The RAMPZ Register in the I/O area is updated in parts\nwith more than 64 KB data space or more than 64 KB program memory, and the increment/decrement/displacement\nis added to the entire 24-bit address on such devices.\nNot all variants of this instruction are available on all devices.\nThe result of these combinations is undefined:\nST Z+, r30\nST Z+, r31\nST -Z, r30\nST -Z, r31\nUsing the Z-pointer: DS(Z+q) ← Rr Z: Unchanged, q:\nDisplacement\nPC ← PC + 1",
"opcode": {
"base": "1000001000000000",
"mask": "1101001000001000"
},
"args": [
{
"name": "r",
"mask": "0000000111110000",
"limits": "0 ≤ r ≤ 31"
},
{
"name": "q",
"mask": "0010110000000111",
"limits": " 0 ≤ q ≤ 63"
}
],
"ops": [
" DS(Z+q) ← Rr Z: Unchanged, q:",
"Displacement",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "2(1)",
"AVRxm": "2(1)",
"AVRxt": "1(2)",
"AVRrc": "N/A"
},
"variant": "(iv)"
},
{
"mnemonic": "STS",
"description": "Stores one byte from a Register to the data space. The data space usually consists of the Register File, I/O memory,\nand SRAM, refer to the device data sheet for a detailed definition of the data space.\nA 16-bit address must be supplied. Memory access is limited to the current data segment of 64 KB. The STS\ninstruction uses the RAMPD Register to access memory above 64 KB. To access another data segment in devices\nwith more than 64 KB data space, the RAMPD in the register in the I/O area has to be changed.\nThis instruction is not available on all devices. Refer to Appendix A. DS(k) ← Rr\nPC ← PC + 2",
"opcode": {
"base": "10010010000000000000000000000000",
"mask": "11111110000011110000000000000000"
},
"args": [
{
"name": "k",
"mask": "00000000000000001111111111111111",
"limits": " 0 ≤ k ≤ 65535"
},
{
"name": "d",
"mask": "00000001111100000000000000000000"
}
],
"ops": [
" DS(k) ← Rr",
"PC ← PC + 2"
],
"cycle_selector": {
"AVRe": 2,
"AVRxm": 2,
"AVRxt": 2,
"AVRrc": "N/A"
}
},
{
"mnemonic": "STS_AVRrc",
"description": "Stores one byte from a Register to the data space. The data space usually consists of the Register File, I/O memory,\nand SRAM, refer to the device data sheet for a detailed definition of the data space.\nA 7-bit address must be supplied. The address given in the instruction is coded to a data space address as follows:\nADDR[7:0] = (INST[8], INST[8], INST[10], INST[9], INST[3], INST[2], INST[1], INST[0])\nMemory access is limited to the address range 0x40...0xbf of the data segment.\nThis instruction is not available on all devices. Refer to Appendix A. (k) ← Rr\nPC ← PC + 1",
"opcode": {
"base": "1010100000000000",
"mask": "1111100000000000"
},
"args": [
{
"name": "k",
"mask": "0000011100001111",
"limits": " 0 ≤ k ≤ 127"
},
{
"name": "d",
"mask": "0000000011110000"
}
],
"ops": [
" (k) ← Rr",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "N/A",
"AVRxm": "N/A",
"AVRxt": "N/A",
"AVRrc": 1
}
},
{
"mnemonic": "SUB",
"description": "Subtracts two registers and places the result in the destination register Rd. Rd ← Rd - Rr\nPC ← PC + 1",
"opcode": {
"base": "0001100000000000",
"mask": "1111110000000000"
},
"args": [
{
"name": "r",
"mask": "0000001000001111",
"limits": " 0 ≤ r ≤ 31"
},
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" Rd ← Rd - Rr",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a borrow from bit 3; cleared otherwise.",
"op": "((~Rd3)&1) & Rr3 | Rr3 & R3 | R3 & ((~Rd3)&1)"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & ((~Rr7)&1) & ((~R7)&1) | ((~Rd7)&1) & Rr7 & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.",
"op": "((~Rd7)&1) & Rr7 | Rr7 & R7 | R7 & ((~Rd7)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SUBI",
"description": "Subtracts a register and a constant, and places the result in the destination register Rd. This instruction is working on\nRegister R16 to R31 and is very well suited for operations on the X, Y, and Z-pointers. Rd ← Rd - K\nPC ← PC + 1",
"opcode": {
"base": "0101000000000000",
"mask": "1111000000000000"
},
"args": [
{
"name": "d",
"mask": "0000000011110000",
"limits": "16 ≤ d ≤ 31"
},
{
"name": "K",
"mask": "0000111100001111",
"limits": " 0 ≤ K ≤ 255"
}
],
"ops": [
" Rd ← Rd - K",
"PC ← PC + 1",
{
"sreg": [
{
"flag": "H",
"description": "Set if there was a borrow from bit 3; cleared otherwise.",
"op": "((~Rd3)&1) & K3 | K3 & R3 | R3 & ((~Rd3)&1)"
},
{
"flag": "S",
"description": " for signed tests.",
"op": "N ^ V"
},
{
"flag": "V",
"description": "Set if two’s complement overflow resulted from the operation; cleared otherwise.",
"op": "Rd7 & ((~K7)&1) & ((~R7)&1) | ((~Rd7)&1) & K7 & R7"
},
{
"flag": "N",
"description": "Set if MSB of the result is set; cleared otherwise.",
"op": "R7"
},
{
"flag": "Z",
"description": "Set if the result is 0x00; cleared otherwise.",
"op": "((~R7)&1) & ((~R6)&1) & ((~R5)&1) & ((~R4)&1) & ((~R3)&1) & ((~R2)&1) & ((~R1)&1) & ((~R0)&1)"
},
{
"flag": "C",
"description": "Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.",
"op": "((~Rd7)&1) & K7 | K7 & R7 | R7 & ((~Rd7)&1)"
}
]
}
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "SWAP",
"description": "Swaps high and low nibbles in a register. R(7:4) ↔ Rd(3:0)\nPC ← PC + 1",
"opcode": {
"base": "1001010000000010",
"mask": "1111111000001111"
},
"args": [
{
"name": "d",
"mask": "0000000111110000",
"limits": "0 ≤ d ≤ 31"
}
],
"ops": [
" R(7:4) ↔ Rd(3:0)",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "WDR",
"description": "This instruction resets the Watchdog Timer. This instruction must be executed within a limited time given by the WD\nprescaler. See the Watchdog Timer hardware specification. WD timer restart.",
"opcode": {
"base": "1001010110101000",
"mask": "1111111111111111"
},
"args": [],
"ops": [
" WD timer restart."
],
"cycle_selector": {
"AVRe": 1,
"AVRxm": 1,
"AVRxt": 1,
"AVRrc": 1
}
},
{
"mnemonic": "XCH",
"description": "Exchanges one byte indirect between the register and data space.\nThe data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the\ncurrent data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the\nRAMPZ in the register in the I/O area has to be changed.\nThe Z-Pointer Register is left unchanged by the operation. This instruction is especially suited for writing/reading\nstatus bits stored in SRAM. DS(Z) ↔ Rd\nPC ← PC + 1",
"opcode": {
"base": "1001001000000100",
"mask": "1111111000001111"
},
"args": [
{
"name": "r",
"mask": "0000000111110000"
}
],
"ops": [
" DS(Z) ↔ Rd",
"PC ← PC + 1"
],
"cycle_selector": {
"AVRe": "N/A",
"AVRxm": 2,
"AVRxt": "N/A",
"AVRrc": "N/A"
}
}
]
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